1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a semiconductor device having a dual-gate.
2. Discussion of Related Art
In general, there are two methods for fabricating a semiconductor device having a dual-gate. The first method is where a dopant implantation for forming gates proceeds simultaneously with a dopant implantation for forming source/drain regions. The second method is where those dopant implantation processes are performed separately.
FIGS. 1A to 1E are cross-sectional views of a portion of a semiconductor device illustrating a process sequence for fabricating the semiconductor device having a dual-gate according to the first method.
In the first method, as illustrated in FIG. 1A, a field oxide film 12 is formed on a silicon substrate 11 using the local oxidation of silicon (LOCOS) technique. Subsequently, a gate insulating film 13 is also formed on the silicon substrate 11. Then, a polysilicon layer 14 is deposited on the field oxide film 12 and the gate insulating film 13. A portion 15 on the left side of the field oxide film 12 is for forming an NMOS transistor while a portion 16 on the right side of the field oxide film 12 is for forming a PMOS transistor.
Thereafter, as illustrated in FIG. 1B, the polysilicon layer 14 is selectively etched to form an NMOS transistor gate 17 and a PMOS transistor gate 18.
Subsequently, as illustrated in FIG. 1C, the right side portion 16 for forming the PMOS transistor is capped with a first photoresist mask 19, and then As.sup.+ (Arsenic) for forming the source/drain lightly doped drain LDD regions is implanted in the left side portion 15.
Then, as illustrated in FIG. 1D, the first mask 19 is removed. At this time, the left side portion 15 is capped with a second mask 20 of photoresist, and then BF.sub.2.sup.+ for forming the source/drain LDD regions is implanted in the right side portion 16.
Thereafter, as illustrated in FIG. 1E, the second mask 20 is removed. At that time, side wall spacers 21 and 22 are formed on both sides of the NMOS transistor gate 17 and the PMOS transistor gate 18, respectively. Subsequently, dopant ions for forming the source/drain regions as well as the gates 17 and 18 are implanted. That is, As.sup.+ (Arsenic) is implanted in the left side portion 15, and, in succession, BF.sub.2.sup.+ is implanted in the right side portion 16.
As described above, in the first semiconductor device fabrication method, the dopant implantation for forming the gates proceeds simultaneously with the dopant implantation for forming the source/drain regions. However, since As.sup.+ (Arsenic) and BF.sub.2.sup.+ are implanted in the NMOS and PMOS transistors, respectively, the threshold voltage Vth varies so that proper device formation is nearly impossible. That is, as a dopant, As.sup.+ (Arsenic) is proper for the NMOS transistor gate while BF.sub.2.sup.+ is proper for the PMOS transistor gate. But, when As.sup.+, (Arsenic) which hardly diffuses, is used as the dopant, the transistor is not sufficiently doped. Furthermore, when BF.sub.2.sup.+ is used as the dopant, the dopant ions diffuse toward the channel. As a result, the threshold voltage seriously varies.
FIGS. 2A to 2D are cross-sectional views of a portion of a semiconductor device illustrating a process sequence for fabricating the semiconductor device having a dual-gate according to the second method.
In the second semiconductor device fabrication method, as illustrated in FIG. 2A, a field oxide film 12 is formed on a silicon substrate 11 using the LOCOS technique. Subsequently, a gate insulating film 13 is formed on the silicon substrate 11. Then, a polysilicon layer 14 is deposited on the field oxide film 12 and the gate insulating film 13. Like the first method, a portion 15 on the left side of the field oxide film 12 is for forming an NMOS transistor while a portion 16 on the right side of the field oxide film 12 is for forming a PMOS transistor.
Subsequently, as illustrated in FIG. 2B, the right side portion 16 is capped with a first photoresist mask 19, and then P.sup.+ (Phosphorous) is implanted in the left side portion 15.
Then, as illustrated in FIG. 2C, the first mask 19 is removed. At this time, the left side portion 15 transistor is capped with a second mask 20 of photoresist, and then B.sup.+ (Boron) is implanted in the right side portion 16.
Thereafter, as illustrated in FIG. 2D, the second mask 20 is removed. At that time, the polysilicon layer 14 is selectively etched to form an NMOS transistor gate 17 and a PMOS transistor gate 18.
Then, the source/drain LDD regions are formed by the general dual-gate formation method.
As described above, in the second semiconductor device fabrication method, when the polysilicon layer 14 for forming the gates is etched, two separate types (N and P types) of ions are implanted in the left side portion 15 and the right side portion 16, respectively. As a result, the surface of the silicon substrate is damaged due to the different etching rates for each side portion.